In recent years, reductions in size, and resistance when driven in high temperature environments, are being demanded of semiconductor devices. Together with this, research and development on semiconductor devices using silicon carbide (SiC) semiconductor bodies (hereafter referred to as silicon carbide semiconductor devices) instead of existing semiconductor devices using silicon (Si) semiconductor bodies is proceeding swiftly. Compared with silicon semiconductors, silicon carbide semiconductor devices have characteristics such that the melting point is higher, and the impurity diffusion coefficient is lower.
In order to fabricate (manufacture) a silicon carbide semiconductor device, it is necessary to, for example, form an Ohmic contact between a silicon carbide semiconductor and a metal electrode film, and to carry out high temperature annealing (high temperature heat treatment) at a temperature exceeding 1,000° C. in order to activate impurities introduced into the silicon carbide semiconductor. For example, furnace annealing using an annealing furnace, and rapid thermal annealing (RTA), are commonly known as annealing (contact annealing) for forming an Ohmic contact between a silicon carbide semiconductor and a metal electrode film.
A description will be given of an existing silicon carbide semiconductor device manufacturing method using furnace annealing or RTA, with an insulated gate field effect transistor (hereafter referred to as a SiC-MOSFET) as an example. FIGS. 10 to 15 are sectional views showing states partway through the manufacture of the existing SiC-MOSFET. Firstly, as shown in FIG. 10, an n−-type SiC epitaxial layer 102, which is to form an n−-type drift region, is grown on the front surface of an n+-type silicon carbide semiconductor substrate (hereafter referred to as an n+-type SiC substrate) 101, which is to form an n+-type drain region.
Next, as shown in FIG. 11, a p-type impurity is ion implanted, thereby selectively forming a p-type base region 103 in a surface layer of the n−-type SiC epitaxial layer 102. Next, as shown in FIG. 12, an n-type impurity ion implantation and a p-type impurity ion implantation are carried out sequentially, thereby selectively forming an n+-type source region 104 and a p+-type contact region 105 in a surface layer of the p-type base region 103. Next, the p-type base region 103, n+-type source region 104, and p+-type contact region 105 are activated using a high temperature annealing at in the region of 1,600° C.
Next, after wet oxidation at a temperature of 1,000° C. in an oxidizing atmosphere, the n−-type SiC epitaxial layer 102 surface is thermally oxidized by post-oxidation annealing (POA) at a temperature of in the region of 1,100° C. in a hydrogen (H2) atmosphere, thereby forming a gate dielectric 106, as shown in FIG. 13. Next, patterning is carried out after depositing a polysilicon (poly-Si) film on the gate dielectric 106, thereby forming a gate electrode 107 across the gate dielectric 106 on a portion of the surface of the p-type base region 103 sandwiched by the n−-type drift region and n+-type source region 104.
Next, as shown in FIG. 14, an interlayer dielectric 108 of PSG (Phosphorus Silicon Glass) or the like is formed so as to cover the gate electrode 107. Next, annealing is carried out at a temperature of in the region of 800° C. for in the region of 10 minutes in order to smoothen (reflow) the interlayer dielectric 108. Next, the interlayer dielectric 108 is selectively removed by etching, thereby forming contact holes for obtaining source contact with the n+-type source region 104 and p+-type contact region 105.
Next, as shown in FIG. 15, a source electrode 109 that comes into contact with the n+-type source region 104 and p+-type contact region 105 via the contact holes is formed. Also, a drain electrode 110 is formed on the back surface of the n+-type SiC substrate 101 simultaneously with the source electrode 109. Next, contact annealing is carried out at a temperature of in the region of 1,000° C. for in the region of 2 minutes, thereby forming an Ohmic contact between the source electrode 109 and a silicon carbide semiconductor and between the drain electrode 110 and a silicon carbide semiconductor. A silicon carbide semiconductor refers to a semiconductor region formed in the n+-type SiC substrate 101 or n−-type SiC epitaxial layer 102.
Next, a one hour post-metallization annealing (PMA) is carried out at a temperature of 400° C., thereby improving the interface characteristics between the gate dielectric 106 and n+-type SiC substrate 101. Subsequently, next, a passivation film (not shown) is formed so as to cover the source electrode 109, thereby completing the SiC-MOSFET. Also, as another annealing to replace the heretofore described furnace annealing and RTA, research and development into laser annealing is being advanced.
A method whereby semiconductor element contact is formed by metal being formed on a silicon carbide substrate, an interface portion of the metal and SiC substrate being annealed, thereby forming a metal-SiC material there, and a certain place on the SiC substrate not being annealed, so that no metal-SiC material is formed there, has been proposed as a method of annealing a metal electrode film formed on an SiC substrate or SiC epitaxial layer using laser annealing (for example, refer to PTL 1).
Also, a method including a step of preparing a silicon carbide substrate having a substrate surface, a step of forming a gate dielectric so as to cover one portion of the substrate surface, a step of forming a contact electrode having Al atoms on the substrate surface so as to be in contact with and neighbor the gate dielectric, a step of forming an alloy having Al atoms by annealing the contact electrode with laser light, and a step of forming a gate electrode that covers one portion of the gate dielectric, has been proposed as another method (for example, refer to PTL 2).